DocumentCode :
1092909
Title :
Device design for the submicrometer p-channel FET with n+polysilicon gate
Author :
Cham, Kit M. ; Chiang, Shang-yi
Author_Institution :
Hewlett-Packard Laboratories, Palo Alto, CA
Volume :
31
Issue :
7
fYear :
1984
fDate :
7/1/1984 12:00:00 AM
Firstpage :
964
Lastpage :
968
Abstract :
CMOS has become one of the most important technologies for VLSI applications. If the conventional n+polysilicon gate approach is to be maintained for VLSI CMOS, the p-channel transistor will cause problems in scaling down to submicrometers due to the counter-doping that is necessary to adjust the threshold voltage to a reasonable value. The depth of the p+source-drain junctions will also cause short-channel effects. This paper presents in-depth analysis of the submicrometer p-channel transistor structure. The effects of the counter-doping junction depth and the source-drain junction depth on the device subthreshold characteristics are discussed. Criteria for the submicrometer p-channel transistor structure with good subthreshold characteristics are presented. A new technique for minimizing the counter-doping junction depth is also presented. Submicrometer p-channel transistors with n+polysilicon gate were fabricated using this new technique as well as techniques for forming very shallow p+-junctions. Devices with submicrometer channel lengths showed very good subthreshold characteristics, as predicted by simulations.
Keywords :
CMOS process; CMOS technology; Circuit synthesis; Doping; Energy consumption; FETs; MOS devices; Predictive models; Threshold voltage; Very large scale integration;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/T-ED.1984.21638
Filename :
1483923
Link To Document :
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