DocumentCode
1093333
Title
Design of GaAs 1k bit static RAM
Author
Ino, Masayuki ; Togashi, Minoru ; Hirayama, Masahiro ; Kurumada, K. ; Ohmori, Masamichi
Author_Institution
Nippon Telegraph and Telephone Public Corporation, Kanagawa, Japan
Volume
31
Issue
9
fYear
1984
fDate
9/1/1984 12:00:00 AM
Firstpage
1139
Lastpage
1144
Abstract
A 1 k bit GaAs static RAM with E/D DCFL was designed and successfully fabricated by SAINT. A bit line pull-up was introduced to the design to make higher operation speed by 25 percent and reduce cell array power consumption by 50 percent. The RAM circuit was optimized in the points of a speed, a power, and an operating margin. A minimum address access time of 1.5 ns was measured for a total power dissipation of 369 mW. This performance is the best achieved so far, for practical application in cache or buffer memories.
Keywords
Analytical models; Circuit simulation; Circuit synthesis; FETs; Gallium arsenide; Parasitic capacitance; Power dissipation; Random access memory; Read-write memory; Threshold voltage;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/T-ED.1984.21677
Filename
1483962
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