An efficient processor for multistage decimation and filtering

An efficient processor for multistage decimation and filtering, utilizing the same IIR digital filter coefficients for all stages, but having a different cutoff frequency at each decimation stage, is presented along with its algorithmic implementation. The upper bound on the decimation ratio per stage is shown to be inversely proportional to the sum of two parameters governing the magnitude response of the IIR low-pass digital filter, while the upper bound on the overall decimation ratio is shown to be proportional to a decimation index. The lower bound on the number of stages is also presented. An example utilizing the proposed algorithm to decimate and filter human colonic electrical control activity is presented.