A photo-patternable stress relief material for plastic packaged integrated circuits

Reports the use of a photo-patternable silicone as an integrated-circuit package stress-relief material. This material is implemented as a final wafer-fabrication masking step over the previously patterned passivation layer. The process uses standard wafer-fabrication equipment and passivation layer masks. The wafers are processed following usual procedures. Results indicate that plastic-packaged circuits which are coated with the photosensitive silicone elastometer exhibit thermal stress test lifetimes that significantly exceed those of non-silicone-coated controls. It is proposed that this technology offers both a potential economy in the assembly process and the potential of overcoming thermal-shock-induced integrated-circuit failures.<>