Title :
20 Gbit/s DR based timing recovery circuit
Author :
Monteiro, P. ; Matos, J.N. ; Gameiro, A. ; Da Roch, J. R F
Author_Institution :
Dept. de Electron. e Telecoms, Aveiro Univ., Portugal
fDate :
5/12/1994 12:00:00 AM
Abstract :
The design and characterisation of a 20 Gbit/s clock recovery unit developed for the RACE 2011 project of the European Community is reported. This unit is based on an open loop structure using a dielectric resonator (DR) narrowband filter. The jitter results show that the approach provides a robust and low cost solution for the clock extraction problem at very high bit rates
Keywords :
dielectric resonators; digital communication systems; optical receivers; passive filters; timing circuits; 20 Gbit/s; DR based circuit; RACE 2011 project; clock extraction; clock recovery unit; dielectric resonator; high bit rates; jitter; narrowband filter; open loop structure; optical fibre links; timing recovery circuit;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19940518
