High-performance embedded branch predictor by combining branch direction history and global branch history

To achieve higher performance in embedded systems, recent embedded microprocessor cores have gradually taken to adopting the technologies of general high-performance microprocessor cores. In branch prediction techniques, usually, the embedded microprocessor cores have used simple bimodal branch predictors. That is, until now, most branch predictors in embedded processor cores have utilised the address of the branch instruction (program counter, PC), and recently some predictors in advanced embedded cores use dynamic branch predictor with global branch history (GBH). The authors suggest branch direction history (BDH) as a new component of the input vector for branch prediction. Additionally, a new embedded branch predictor is proposed, called direction-gshare predictor, which utilises BDH information, as an implementation example. In simulation parts, a neural network with three branch prediction input vectors (PC, GBH and BDH) is modelled and their actual impact upon the branch prediction accuracy is analysed. Then, the new embedded branch predictor, the direction-gshare predictor is simulated. The simulation results show that the aliasings in pattern history table are reduced, 48.9% on average, by the additional use of BDH information. Moreover, the direction-gshare predictor outperforms previous embedded branch predictors, such as bimodal predictor, two-level adaptive predictor and gshare predictor, up to 15.32%, 5.41% and 5.74%, respectively.