Title :
Design tradeoffs between surface and buried-channel FET´s
Author :
Hu, Genda J. ; Bruce, Richard H.
Author_Institution :
Sierra Semiconductor Corporation, Sunnyvale, CA
fDate :
3/1/1985 12:00:00 AM
Abstract :
A study of the operation of surface- and buried-mode p-channel FET´s is conducted. The buried-channel devices are fabricated using n-type polysilicon gates while the surface-channel devices employ p-type polysilicon gates. Using devices with different channel lengths (20 to 0.4 µm), threshold voltage lowering, subthreshold characteristics, transconductance, punchthrough, and body effects are compared over a wide range of background doping concentrations. In the study surface-channel devices were found to be more resistant to short-channel effects than their buried-channel counterparts independent of background doping concentration. Two-dimensional computer simulation revealed that buried-channel devices are more subject to drain-induced barrier lowering and bulk punchthrough. The body effect for the surface-channel device is lower than its counterpart at low background doping concentrations whereas the buried-channel device has a lower body effect at high background doping levels. The effective carrier mobility of buried-channel devices was found greater than that of surface devices. The net difference in the transconductance, however, is offset by the high parasitic diffusion resistance.
Keywords :
Boron; CMOS technology; Capacitance-voltage characteristics; Doping; FETs; Fabrication; Implants; Silicon; Threshold voltage; Voltage measurement;
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/T-ED.1985.21981