DocumentCode
1099273
Title
Current polarity switching decoders for Josephson memory arrays
Author
Nakanishi, Takuji ; Fujita, S.
Author_Institution
Nippon Telegraph and Telephone, Public Corporation, Atsugi-shi, Kanagawa, Japan
Volume
32
Issue
3
fYear
1985
fDate
3/1/1985 12:00:00 AM
Firstpage
610
Lastpage
616
Abstract
Two new types of Josephson decoder circuits have been devised, designed, fabricated, and tested. The circuits utilize current polarities along address loops as information. This results in simple circuit configurations with about half the number of circuit gates than conventional Josephson decoder circuits. This contributes to improved yield rates and to a decrease in circuit area. One of the two decoder circuitsz described in this paper can be operated with either dc or unipole while the other is unipole only. Using computer simulation, the operating speed for the former 5-32 decoder circuit is about 320 ps which is almost the same as that of conventional decoders, while for the latter circuit it is 115 ps which is almost half of that for the conventional decoders. The decoders are designed with operating margins of over ±35 percent which is sufficient for Josephson circuits. Critical path subsections of these two 5-32 decoder circuits were fabricated by standard lead-alloy technology and quasi-staticaUy operated successfully.
Keywords
Circuit testing; Communication switching; Computer simulation; Decoding; Delay; Flip-flops; High speed integrated circuits; Inductance; Space technology; Switching circuits;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/T-ED.1985.21986
Filename
1484732
Link To Document