Title :
The dynamics of latchup turn-on behavior in scaled CMOS
Author :
Odanaka, Shinji ; Wakabayashi, M. ; Ohzone, Takashi
Author_Institution :
Matsushita Electric Industrial Company, Ltd., Osaka, Japan
fDate :
7/1/1985 12:00:00 AM
Abstract :
This paper presents the dynamics of latchup turn-on behavior in scaled CMOS structures using an exact time-dependent and two-dimensional numerical analysis based on the finite-difference approach. Both the dynamics of surface-induced latchup triggering by a parasitic PMOSFET and direct forward biasing are examined to discuss the two-dimensional effects of parasitic devices in a scaled CMOS structure during latchup turn-on. In the case of an n-well scaled CMOS, the two-dimensional nature of the well structure plays an important role for surface-induced latchup.
Keywords :
Analytical models; Charge carrier processes; Electrostatics; Finite difference methods; Helium; MOSFET circuits; Numerical analysis; Numerical simulation; Poisson equations; Semiconductor device modeling;
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/T-ED.1985.22120