• DocumentCode
    1101697
  • Title

    A comparison of fine-dimension silicon-on-sapphire and bulk-silicon complementary MOS devices and circuits

  • Author

    Brassington, Michael P. ; Lewis, Alan G. ; Partridge, Susan L.

  • Author_Institution
    Fairchild Camera and Instrument Corp., Palo Alto, CA
  • Volume
    32
  • Issue
    9
  • fYear
    1985
  • fDate
    9/1/1985 12:00:00 AM
  • Firstpage
    1858
  • Lastpage
    1867
  • Abstract
    The fabrication of fine-dimension silicon-gate MOS devices on both silicon-on-sapphire and bulk-silicon substrates has made possible a direct comparison of the electrical characteristics of devices based on these technologies. The same CMOS test chip design was used in both cases and provided both n- and p-channel devices having gate dimensions ranging down to submicrometer levels. Extensive electrical evaluation of the resulting devices has enabled quantitative comparison of carrier mobilities, short- and narrow-channel threshold voltage shifts, punchthrough, and subthreshold characteristics for SOS and bulk-silicon technologies. The effect of epitaxial film thickness on these properties for SOS devices is also discussed. An anomalous narrow-channel threshold voltage shift effect is observed in SOS devices and explained in terms of parasitic device characteristics. The general conclusion based on the observations made is that short-and narow-channel effects in SOS devices are significantly less of a problem than in bulk silicon devices at these gate dimensions. The direct comparison of the dynamic performance of SOS and bulk CMOS circuits can be obscured, for example by differences in gate oxide thickness and threshold voltages. In this case, however, both gate oxide thickness and threshold voltages have been closely matched. This, together with the fact that the circuits were fabricated by the same processing facility using the same chip design, should increase the reliability of any comparison. The results have indicated that at 1-µm dimensions the propagation delay of SOS CMOS circuits is 60 percent lower than that of equivalent bulk-silicon CMOS circuits.
  • Keywords
    CMOS technology; Chip scale packaging; Circuit testing; Electric variables; Fabrication; MOS devices; Propagation delay; Silicon devices; Substrates; Threshold voltage;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/T-ED.1985.22209
  • Filename
    1484955