Optimized design of a merged bipolar MOSFET device

Numerical techniques have been applied to predict the steady-state characteristics of lateral bipolar-MOSFET (BIMOS) power switching devices. The BIMOS has the same structure as a lateral double-diffused MOSFET (LDMOS), with the p-type channel region acting as the base of an n-p-n transistor. By merging MOSFET and bipolar transistors in a lateral configuration, a monolithic power-integrated circuit is realized which retains some of the desirable features of both types of transistors for switching applications. Specifically, the structure of a switching device with low on-resistance high voltage capability, fast switching speed, and high input impedance is derived which does not require significantly increased device fabrication complexity. A special junction isolation design was used to limit the parasitic effects involving the substrate. These parasitic effects can degrade the performance of the BIMOS by reducing the gain of the n-p-n transistor and introducing a large substrate current. An off-state model has been developed in order to study the field shaping effects which occur with the inclusion of the junction isolation. The design is optimized to obtain a high-breakdown-voltage low-on-resistance parasitic-free monolithic-power integrated circuit.