Universal NBTI Compact Model for Circuit Aging Simulation under Any Stress Conditions

Author

Chenyue Ma ; Mattausch, Hans Jurgen ; Matsuzawa, K. ; Yamaguchi, Satarou ; Hoshida, Takeshi ; Imade, M. ; Koh, R. ; Arakawa, Takeshi ; Miura-Mattausch, M.

Author_Institution

Grad. Sch. of Adv. Sci. of Matter, Hiroshima Univ., Hiroshima, Japan

Volume

14

Issue

3

fYear

2014

fDate

Sept. 2014

Firstpage

818

Lastpage

825

Abstract

In this paper, a compact model for the negative bias temperature instability (NBTI) is developed by considering the interface-state generation and the hole-trapping mechanisms. This model shows accurate reproduction of the threshold voltage (V_th) degradations measured from samples fabricated with different dielectric materials as well as processes. A total of eight model parameters are introduced for describing the different degradation origins. The parameter values are verified to exhibit universal properties as a function of the electrical field within the gate oxide (E_ox). By implementing the universal NBTI model into the compact model HiSIM, the dynamic NBTI effect and circuit performance degradation can be predicted.

Keywords

MOSFET; ageing; circuit simulation; dielectric materials; hole traps; interface states; negative bias temperature instability; semiconductor device models; circuit aging simulation; compact model HiSIM; dielectric material; electrical field; gate oxide; hole-trapping mechanism; interface-state generation; negative bias temperature instability; pMOSFET; stress condition; threshold voltage measurement; universal NBTI compact model; Data models; Degradation; Dielectric measurement; Integrated circuit modeling; Interface states; Logic gates; Stress; Negative bias temperature instability (NBTI); hole-trapping; interface-state; modeling; universality;

fLanguage

English

Journal_Title

Device and Materials Reliability, IEEE Transactions on

Publisher

ieee

ISSN

1530-4388

Type

jour

DOI

10.1109/TDMR.2014.2322673

Filename

6812162