Abstract :
In keeping with the experimental nature of the Illinois Pattern Recognition Computer (ILLIAC III), the arithmetic units are intended to be a practical testing ground for recent theoretical work in computer arithmetic. This paper describes the use of redundant number systems and the design of a structure with which multiplication and division are executed radix 256. The heart of the unit is the stored-sign subtracter, a recently discovered member of the family of borrow-save subtracters and carry-save adders. A cascade of these subtracters, controlled by a multiplier recoder, provides multiplication. The same structure, controlled by a "model division" (a quotient recoder), performs division.
Keywords :
Arithmetic unit, computer arithmetic, division, higher radix arithmetic, ILLIAC III, multiplication, redundant number systems, signed-digit subtracter, stored-sign subtracter.; Adders; Computer science; Design methodology; Digital arithmetic; Floating-point arithmetic; Heart; Logic design; Military computing; Pattern recognition; Testing; Arithmetic unit, computer arithmetic, division, higher radix arithmetic, ILLIAC III, multiplication, redundant number systems, signed-digit subtracter, stored-sign subtracter.;
