An Improved Two-Step Binary Logarithmic Converter for FPGAs

This brief describes an improved binary linear-to-log (Lin2Log) conversion algorithm that has been optimized for implementation on a field-programmable gate array. The algorithm is based on a piecewise linear (PWL) approximation of the transform curve combined with a PWL approximation of a scaled version of a normalized segment error. The architecture presented achieves 23 bits of fractional precision while using just one 18K-bit block RAM (BRAM), and synthesis results indicate operating frequencies of 93 and 110 MHz when implemented on Xilinx Spartan3 and Spartan6 devices, respectively. Memory requirements are reduced by exploiting the symmetrical properties of the normalized error curve, allowing it to be more efficiently implemented using the combinatorial logic available in the reconfigurable fabric instead of using a second BRAM inefficiently. The same principles can be also adapted to applications where higher accuracy is needed.