• DocumentCode
    1106301
  • Title

    Synthesis of Networks with a Minimum Number of Negative Gates

  • Author

    Ibaraki, Toshihide ; Muroga, Saburo

  • Author_Institution
    IEEE
  • Issue
    1
  • fYear
    1971
  • Firstpage
    49
  • Lastpage
    58
  • Abstract
    In this paper we develop an algorithm to design a switching network using only gates which represent negative functions. The number of gates in the network is minimized under the conditions that 1) the network consists of two levels, and 2) no fan-in restriction on each gate is imposed.
  • Keywords
    Conjoint, logical design, minimal cover, MOS, negative gates, network with minimum number of gates, supplementary columns, truth table.; Algorithm design and analysis; Computer science; FETs; Input variables; Integrated circuit technology; MOS integrated circuits; Manufacturing; Minimization; Network synthesis; Power dissipation; Conjoint, logical design, minimal cover, MOS, negative gates, network with minimum number of gates, supplementary columns, truth table.;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/T-C.1971.223081
  • Filename
    1671674
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1106301