Fast Identification of Critical Electrical Disturbs in Nonvolatile Memories

We propose a new methodology for a fast top-down identification of disturbs in large arrays of nonvolatile memories. The new strategy aims at providing the set of all the effective and dangerous disturbs present in a technology with no a priori selection of the physical mechanisms to be targeted. No simulations are needed, and neighbor-cell influence on disturb is empirically taken into account. This top-down strategy requires a limited set of experimental measurements and provides, in a fast "one-shot" approach, a complete disturb assessment, including the effects of new failure mechanisms. Experimental results on nonconventional floating gate Flash test chips are shown and discussed in order to demonstrate the features and the validity of the proposed methodology.