Vertically Stacked Carbon Nanotube-Based Interconnects for Through Silicon Via Application

Author

Di Jiang ; Wei Mu ; Si Chen ; Yifeng Fu ; Jeppson, Kjell ; Liu, Johan

Author_Institution

Dept. of Microtechnol. & Nanosci., Chalmers Univ. of Technol., Gothenburg, Sweden

Volume

36

Issue

5

fYear

2015

fDate

May-15

Firstpage

499

Lastpage

501

Abstract

Stacking of silicon chips with carbon nanotube (CNT)-based through-silicon vias (TSVs) is experimentally demonstrated. Polymer filling is used to improve the transfer quality of CNTs into pre-etched silicon holes. Special hexagonal CNTs are designed to achieve high aspect ratio (10:1) CNT vias. TSVs filled with closely packed CNTs show a highly linear dc I-V response. The proposed process works at room temperature, which makes it compatible with existing device fabrication flow.

Keywords

carbon nanotubes; integrated circuit interconnections; three-dimensional integrated circuits; CNT; TSV; device fabrication flow; linear dc I-V response; polymer filling; pre-etched silicon holes; silicon chips; temperature 293 K to 298 K; through silicon via application; transfer quality; vertically stacked carbon nanotube-based interconnects; Arrays; Carbon nanotubes; Fabrication; Polymers; Resistance; Silicon; Through-silicon vias; 3D Stacking; 3D stacking; Carbon Nanotube (CNT); Carbon nanotube (CNT); Densification; Interconnect; Through-silicon via (TSV); Transfer; densification; interconnect; through-silicon via (TSV); transfer;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2015.2415198

Filename

7064733