Synthesis of efficient pipelined architectures for implementing DSP operations

A theoretical study is presented of the synthesis of the most efficient pipelined processing system for executing a digital signal processing (DSP) algorithm. The results provide the conditions for determining the most efficient mapping of DSP algorithms to the processing elements of a processor. This is achieved by allocating the various arithmetic and data transfer operations of the algorithm to the processing elements of the system in such a manner that all basic components are concurrently active throughout the entire operation. Pipelining and parallel processing at each stage of the pipeline is used to achieve the best possible performance. Applications of the results to the design of FFT-processors are also included. Finally, the results are used to demonstrate how the overall problem can be reformulated as an optimization problem to minimize a cost function of the system under certain constraints.