Title :
Optimum clustering for delay minimization
Author :
Rajaraman, Rajmohan ; Wong, D.F.
Author_Institution :
Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
fDate :
12/1/1995 12:00:00 AM
Abstract :
This paper addresses the problem of circuit clustering for delay minimization, subject to area capacity constraints. We use the general delay model, for which only heuristic solutions were known. We present an optimum polynomial-time algorithm for combinational circuits under this model. Our algorithm can be generalized to solve the problem under any monotone clustering constraint
Keywords :
circuit optimisation; combinational circuits; delays; logic partitioning; minimisation; area capacity; combinational circuits; delay minimization; optimum clustering; polynomial-time algorithm; Clustering algorithms; Combinational circuits; Computer networks; Delay; Integrated circuit interconnections; Labeling; Minimization methods;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
