Title :
A new self-aligned well-isolation technique for CMOS devices
Author :
Suyama, Shiro ; Yachi, Toshiaki ; Serikawa, Tadashi
Author_Institution :
Nippon Telegraph and Telephone Corporation, Tokyo, Japan
fDate :
11/1/1986 12:00:00 AM
Abstract :
This paper presents the development of a new well-isolation technique for advanced CMOS LSI´s. The technique comprises narrow deep trench fabrication utilizing undercut, in addition to silicon-oxide cap formation, which leaves a cavity. The predominant feature of this technique is that well isolation self-aligned to the well region is realized utilizing the trench fabrication technique. Additionally, no crystal defects are observed around the well isolation even after 1000°C annealing following silicon-oxide cap formation. Since the well isolation produced also prevents the latchup phenomenon from occurring due to its depth, this technique enables the CMOS device dimensions to be considerably reduced.
Keywords :
Aluminum; Anisotropic magnetoresistance; Annealing; CMOS technology; Etching; Fabrication; Lithography; Semiconductor films; Silicon; Substrates;
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/T-ED.1986.22727