Title :
Sign extension bit minimisation algorithm for multi-bit coded multiplier structures for DSP applications
Author_Institution :
Indian Telephone Ind. Ltd., Bangalore, India
fDate :
8/1/1996 12:00:00 AM
Abstract :
A novel algorithm for minimising the sign extension bits involved in the design of VLSI multi-bit coded multiplier and multiplier-accumulator arithmetic modules is described. Design examples are presented to illustrate the flexibility of the proposed algorithm
Keywords :
VLSI; digital arithmetic; digital signal processing chips; minimisation; multiplying circuits; DSP applications; VLSI multi-bit coded multiplier; multi-bit coded multiplier structures; multiplier-accumulator arithmetic modules; sign extension bit minimisation algorithm;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19961007
