Application of Uniform Loading Theory to Circuit Packaging and Memory Arrays in High-Speed Computers

Author

Hou, Hsieh S.

Author_Institution

Xerox Data Systems

Issue

5

fYear

1972

fDate

5/1/1972 12:00:00 AM

Firstpage

454

Lastpage

463

Abstract

The uniform loading theory [1] has been approximated and used to analyze a class of interconnection problems usually encountered in the design of high-speed circuit packaging and memory arrays in today´s computers. The uniform loads are, for example, IC gates and via holes on multilayered printed circuit board and cross-coupling capacitance in memory arrays. They are treated as discrete loads along smooth transmission lines. The input and output transfer function, impulse response, unit step response, and propagation delay are calculated. To a first-order approximation, the pure resistive loaded line impedance and voltage reflection coefficient can be easily derived. Matching conditions and some experimental results are included. Oscillation due to second-order effects is also discussed.

Keywords

Coupling between word line and digit line, equivalent circuit of via hole, IC gate loading, impulse response of uniform loaded line, loaded impedance, propagation delay of uniform loaded line.; Application software; Capacitance; Circuit analysis computing; Distributed parameter circuits; Integrated circuit interconnections; Packaging; Printed circuits; Propagation delay; Transfer functions; Transmission line theory; Coupling between word line and digit line, equivalent circuit of via hole, IC gate loading, impulse response of uniform loaded line, loaded impedance, propagation delay of uniform loaded line.;

fLanguage

English

Journal_Title

Computers, IEEE Transactions on

Publisher

ieee

ISSN

0018-9340

Type

jour

DOI

10.1109/T-C.1972.223541

Filename

1672134