DocumentCode
1111016
Title
A Deductive Method for Simulating Faults in Logic Circuits
Author
Armstrong, Douglas B.
Author_Institution
Bell Telephone Laboratories, Inc.
Issue
5
fYear
1972
fDate
5/1/1972 12:00:00 AM
Firstpage
464
Lastpage
471
Abstract
A deductive method of fault simulation is described, which "deduces" the faults defected by a test at the same time that it simulates explicitly only the good behavior of logic circuit. For large logic circuits (at least several thousand gates) it is expected to be faster than "parallel" fault simulators, but uses much more computer memory than do parallel simulators.
Keywords
Deductive method, error symptoms, fault dictionary, fault simulation, logic circuits, simulation, trouble location.; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Computer simulation; Concurrent computing; Electrical fault detection; Fault detection; Logic circuits; Logic testing; Deductive method, error symptoms, fault dictionary, fault simulation, logic circuits, simulation, trouble location.;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/T-C.1972.223542
Filename
1672135
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