Title :
Power estimation techniques for FPGAs
Author :
Anderson, Jason H. ; Najm, Farid N.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Toronto, Ont., Canada
Abstract :
The dynamic power consumed by a digital CMOS circuit is directly proportional to both switching activity and interconnect capacitance. In this paper, we consider early prediction of net activity and interconnect capacitance in field-programmable gate array (FPGA) designs. We develop empirical prediction models for these parameters, suitable for use in power-aware layout synthesis, early power estimation/planning, and other applications. We examine how switching activity on a net changes when delays are zero (zero delay activity) versus when logic delays are considered (logic delay activity) versus when both logic and routing delays are considered (routed delay activity). We then describe a novel approach for prelayout activity prediction that estimates a net´s routed delay activity using only zero or logic delay activity values, along with structural and functional circuit properties. For capacitance prediction, we show that prediction accuracy is improved by considering aspects of the FPGA interconnect architecture in addition to generic parameters, such as net fanout and bounding box perimeter length. We also demonstrate that there is an inherent variability (noise) in the switching activity and capacitance of nets that limits the accuracy attainable in prediction. Experimental results show the proposed prediction models work well given the noise limitations.
Keywords :
CMOS digital integrated circuits; electronic engineering computing; field programmable gate arrays; integrated circuit design; integrated circuit interconnections; integrated circuit noise; low-power electronics; FPGA design; FPGA interconnect architecture; capacitance prediction; digital CMOS circuit; dynamic power consumption; electronic engineering computing; field programmable gate array; interconnect capacitance; logic delay activity; noise limitations; power aware layout synthesis; power estimation; prediction models; switching activity; zero delay activity; Accuracy; CMOS digital integrated circuits; Capacitance; Delay estimation; Field programmable gate arrays; Integrated circuit interconnections; Logic; Predictive models; Semiconductor device modeling; Switching circuits;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2004.831478