Title :
A simple method to improve the noise margin of III-V DCFL Digital circuit coupling diode FET logic
Author :
Yang, Long ; Yuen, Albert T. ; Long, Stephen I.
Author_Institution :
University of California, Santa Barbara, CA
fDate :
3/1/1986 12:00:00 AM
Abstract :
This paper proposes a novel method to increase the noise margins achievable with III-V DCFL digital circuits. The idea is to increase the forward-biased potential obtainable on the gate of the enhancement device before substantial conduction occurs. The method we propose is to simply add a diode in series with the gate. Circuit simulations (MESFET and HFET) and device theory are given to support the feasibility of the Coupling Diode FET Logic (CDFL). A novel device structure, compatible with the semiconductor-gate HFET [3], also will be given.
Keywords :
Circuit noise; Coupling circuits; Digital circuits; FETs; HEMTs; III-V semiconductor materials; Logic circuits; Logic devices; Semiconductor device noise; Semiconductor diodes;
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/EDL.1986.26326
