DocumentCode :
1112709
Title :
Lookaside Techniques for Minimum Circuit Memory Translators
Author :
Carter, William C. ; Duke, Keith A. ; Jessep, Donald C., Jr.
Author_Institution :
T. J. Watson Reserch Center, IBM Corporation
Issue :
3
fYear :
1973
fDate :
3/1/1973 12:00:00 AM
Firstpage :
283
Lastpage :
289
Abstract :
This paper demonstrates two improvements in coding techniques that could be used for memory word coding. First, within the fixed structure of a Hamming single-error-correcting, double-error-detecting (SEC/DED) code, an improvement can be obtained in circuit cost and operational speed over more conventional code implementations. Second, the mechanics of error correction in a fault-tolerant computer may be carried out via conventional hardware means or by use of the existing system facilities, such as the combination of the microprogram unit, local store, and the arithmetic-logic unit. These improvements may be obtained by the use of Rotational Coding schemes in conjunction with a technique calied "lookaside correction." This paper first shows a generalized algorithm for specifying the parity check matrix of Rotational Codes. The structure implemented by the parity check matrix in this paper is not merely encoding and decoding circuitry, but translates between Rotational Code forms and byte-parity encoded forms. The unique feature of these translators is that use of the Rotational Code permits the error correction to be performed on only a subset of the data word bits, and only if a single-error condition has been detected. The correction mechanism may be either a hardware logic circuit or firmware. The paper concludes with a comparison of the circuit requirements and correctional speed of the Hamming (72, 64) single-error-correcting, double-error-detecting code, as it normally would be implemented, and a Rotational Code translator also operating on 64 data bits and 8 check bits.
Keywords :
Decoding, encoding, error correction, error detection, translators.; Costs; Decoding; Encoding; Error correction; Error correction codes; Fault tolerant systems; Hardware; Logic circuits; Microprogramming; Parity check codes; Decoding, encoding, error correction, error detection, translators.;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/T-C.1973.223708
Filename :
1672301
Link To Document :
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