DocumentCode
1115167
Title
Fault Detection of Binary Sequential Machines Using R-Valued Test Machines
Author
Sheppard, Donald A. ; Vranesic, Zvonko G.
Author_Institution
Cybernetic Services, Canadian National Railway
Issue
4
fYear
1974
fDate
4/1/1974 12:00:00 AM
Firstpage
352
Lastpage
358
Abstract
An improved method for detection of faults in completely specified synchronous sequential machines is described. The technique is algorithmic, based on the concept of embedding the given binary machine into an easily testable R-valued machine. Heuristic optimization of additional permutation inputs is shown to lead to considerable reduction in the length of the fault sequence. A bound on the sequence length is derived, which in most cases is significantly lower than those of comparable methods.
Keywords
Fault detection, many-valued logic, permutation inputs, synchronous sequential machines, test machines.; Circuit faults; Circuit testing; Councils; Cybernetics; Fault detection; Logic circuits; Logic testing; Multivalued logic; Rail transportation; Sequential analysis; Fault detection, many-valued logic, permutation inputs, synchronous sequential machines, test machines.;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/T-C.1974.223949
Filename
1672542
Link To Document