Title :
A comprehensive study on the FIBL of nanoscale MOSFETs
Author :
Tsui, Bing-Yue ; Chin, Li-Feng
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao-Tung Univ., Hsinchu, Taiwan
Abstract :
Fringing-induced barrier lowering (FIBL) effect on nanoscale MOSFET is comprehensively examined. It is observed that by combining stack gate dielectric, conductive spacer, short sidewall spacer, and minimum gate/drain (G/D) overlap, the Ioff with a dielectric constant of (k) 100 is only 1.6 times higher than that with k=3.9 when the gate length is 25 nm. The fully depleted silicon-on-insulator device shows even better FIBL immunity. It is concluded that although the FIBL effect can not be eliminated, it would not an issue beyond the 45-nm technology node.
Keywords :
MOSFET; dielectric thin films; nanoelectronics; silicon-on-insulator; 25 nm; FIBL effect; FIBL immunity; SOI device; combining stack gate dielectric; conductive spacer; fringing-induced barrier lowering; high dielectric constant material; minimum drain; minimum gate; nanoscale MOSFET; short sidewall spacer; silicon-on-insulator; Degradation; Dielectric constant; Dielectric devices; Dielectric materials; Doping profiles; High-K gate dielectrics; MOSFETs; Silicon compounds; Silicon on insulator technology; Threshold voltage; FIBL; Fringing-induced barrier lowering; MOSFET; SOI; high dielectric constant material; silicon-on-insulator; stack gate dielectric;
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/TED.2004.835022
