An Efficient SVPWM Algorithm With Low Computational Overhead for Three-Phase Inverters

A compact algorithm of space vector pulsewidth modulation (SVPWM) for three-phase inverters is proposed and developed in this paper. Simplified by the proposed method, the conventional SVPWM is decomposed into fast integer operations entirely by using an intermediate vector, which will properly counteract the redundant calculations of the remaining procedures. This concept can not only simplify a two-level scheme, but is also suited for multilevel implementation. Since it can be implemented without any multiplier or divider, the fast algorithm is especially suitable for field programmable gate array applications. Then, an area- and speed-efficient IP-core based on this algorithm is built and tested. It ensures lower hardware resource usage, and at the same time, operates several times faster than some reported examples. Finally, experimental results obtained from a dc-ac inverter prototype are presented to verify the viability and effectiveness of the proposed algorithm.