DocumentCode :
1116833
Title :
A Probabilistic Approach of Designing More Reliable Logic Gates with Asymmetric Input Faults
Author :
Hu, Sung C.
Author_Institution :
Department of Electrical Engineering, Cleveland State University
Issue :
10
fYear :
1975
Firstpage :
1012
Lastpage :
1014
Abstract :
Logic gates subject to asymmetric input faults may be made more reliable by employing redundant inputs. A mathematical expression for determining the optimum number of redundant inputs based on input reliabilities of the gate is developed. The development follows the theory of combinatorial probability.
Keywords :
Asymmetric input-faults, input redundancy, logic gate, probability, reliability.; Circuit faults; Circuits and systems; Digital systems; Fault tolerant systems; Integrated circuit reliability; Logic circuits; Logic design; Logic gates; Probabilistic logic; Redundancy; Asymmetric input-faults, input redundancy, logic gate, probability, reliability.;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/T-C.1975.224113
Filename :
1672706
Link To Document :
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