DocumentCode :
1117798
Title :
Hazard Correction in Synchronous Sequential Circuits
Author :
Servít, Michal
Author_Institution :
Department of Computers, Electrotechnical Faculty, Czech Polytechnical Institute
Issue :
3
fYear :
1975
fDate :
3/1/1975 12:00:00 AM
Firstpage :
305
Lastpage :
310
Abstract :
Limitations which are placed on input and clock signals of single and double-rank synchronous sequential circuits with memory composed of level-triggered flip-flops are presented and compared with the results of Unger [1] and Curtis [2].
Keywords :
Double-rank circuit, flip-flop memory, hazard correction, single-rank circuit, synchronous sequential circuit.; Clocks; Delay effects; Flip-flops; Hazards; Logic; Sequential circuits; Space vector pulse width modulation; Strontium; Sufficient conditions; Synchronization; Double-rank circuit, flip-flop memory, hazard correction, single-rank circuit, synchronous sequential circuit.;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/T-C.1975.224211
Filename :
1672804
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=1117798
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