Precise analog synapse for Kohonen feature maps

Author

Heim, P. ; Vittoz, E.A.

Author_Institution

Lab. d´´Electron. Gen., Ecole Polytech. Federale de Lausanne, Switzerland

Volume

29

Issue

8

fYear

1994

fDate

8/1/1994 12:00:00 AM

Firstpage

982

Lastpage

985

Abstract

A plastic medium-term analog synapse is presented that fulfils the stringent specifications necessary for the Kohonen algorithm. The principle is based on a switched capacitor-like technique implementing a variable time-constant integrator. The memory leakage standard deviation is 2 mV/s for a voltage range of 2 V at room temperature and the learning gain can be varied over two decades. Its differential structure leads to good CMRR, PSRR, and charge injection cancellation. The total synapse area is &frac116; mm² using a 3-μm self-aligned contact single-metal CMOS technology. Measurement results of a test chip are also presented

Keywords

CMOS integrated circuits; analogue processing circuits; integrating circuits; learning (artificial intelligence); linear integrated circuits; neural chips; self-organising feature maps; 2 V; 3 micron; CMRR; Kohonen feature maps; PSRR; charge injection cancellation; differential structure; learning gain; memory leakage standard deviation; precise analog synapse; self-aligned contact single-metal CMOS technology; switched capacitor-like technique; variable time-constant integrator; Analog circuits; CMOS technology; Circuit testing; Clustering algorithms; Hardware; Pattern classification; Plastics; Semiconductor device measurement; Temperature distribution; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.297708

Filename

297708