Optimization of gate oxide N2O anneal for CMOSFET´s at room and cryogenic temperatures

This paper presents a study of the impact of gate-oxide N₂ O anneal on CMOSFET´s characteristics, device reliability and inverter speed at 300 K and 85 K. Two oxide thicknesses (60 and 110 Å) and five N₂O anneal conditions (900~950°C, 5~40 min) plus nonnitrided process and channel lengths from 0.2 to 2 μm were studied to establish the correlation between the nitrogen concentration at Si/SiO₂ interface and the relative merits of the resultant devices. We concluded that one simple post-oxidation N₂O anneal step can increase CMOSFET´s lifetime by 4~10 times, effectively suppress boron penetration from the P⁺ poly-Si gate of P-MOSFET´s without sacrificing CMOS inverter speed. We also found that the benefits in terms of the improved interface hardness and charge trapping characteristic still exist at cryogenic temperature. All these improvements are found to be closely correlated to the nitrogen concentration incorporated at the Si/SiO₂ interface. The optimal N₂O anneal occurs somewhere at around 2% of nitrogen incorporation at Si/SiO₂ interface which can be realized by annealing 60~110 Å oxides at 950°C for 5 min or 900°C for 20 min