Hysteresis I-V effects in short-channel Silicon MOSFET´s

Hysteresis in Ids-Vdscharacteristics is observed at high drain voltages in short-channel silicon MOSFET´s biased into the normally off regime, the degree of which depends on the substrate and gate biases. The MOSFET switches at this hysteresis point from subthreshold to space-charge limited current behavior. It is proposed that this hysteresis effect is due to avalanched holes which accumulate at the gate interface, causing a deformation of the potential distribution in the substrate and the triggering of the device into space-charge limited current behavior.