• DocumentCode
    1121503
  • Title

    Design and experimental technology for 0.1-µm gate-length low-temperature operation FET´s

  • Author

    Sai-Halasz, George A. ; Wordeman, Matthew R. ; Kern, D.P. ; Ganin, E. ; Rishton, S. ; Zicherman, D.S. ; Schmid, H. ; Polcari, Michael R. ; Ng, H.Y. ; Restle, P.J. ; Chang, T.H.P. ; Dennard, Robert H.

  • Author_Institution
    IBM Thomas J. Watson Research Center, Yorktown Heights, NY
  • Volume
    8
  • Issue
    10
  • fYear
    1987
  • fDate
    10/1/1987 12:00:00 AM
  • Firstpage
    463
  • Lastpage
    466
  • Abstract
    The first device performance results are presented from experiments designed to assess FET technology feasibility in the 0.1-µm gate-length regime. Low-temperature device design considerations for these dimensions lead to a 0.15-V threshold and 0.6-V power supply, with a forward-biased substrate. Self-aligned and almost fully scaled devices and simple circuits were fabricated by direct-write electron-beam lithography at all levels, with gate lengths down to 0.07 µm. Measured device characteristics yielded over 750-mS/mm transconductance, which is the highest value obtained to date in Si FET´s.
  • Keywords
    Degradation; FET integrated circuits; Insulation; Integrated circuit measurements; Integrated circuit yield; Power supplies; Temperature; Transconductance; Tunneling; Voltage;
  • fLanguage
    English
  • Journal_Title
    Electron Device Letters, IEEE
  • Publisher
    ieee
  • ISSN
    0741-3106
  • Type

    jour

  • DOI
    10.1109/EDL.1987.26695
  • Filename
    1487245