• DocumentCode
    112195
  • Title

    Median Filter Architecture by Accumulative Parallel Counters

  • Author

    Cadenas, J.O. ; Megson, G.M. ; Sherratt, R.S.

  • Author_Institution
    Sch. of Syst. Eng., Univ. of Reading, Reading, UK
  • Volume
    62
  • Issue
    7
  • fYear
    2015
  • fDate
    Jul-15
  • Firstpage
    661
  • Lastpage
    665
  • Abstract
    The time to process each of the W/B processing blocks of a median calculation method on a set of N W-bit integers is improved here by a factor of three compared with literature. The parallelism uncovered in blocks containing B-bit slices is exploited by independent accumulative parallel counters so that the median is calculated faster than any known previous method for any N, W values. The improvements to the method are discussed in the context of calculating the median for a moving set of N integers, for which a pipelined architecture is developed. An extra benefit of a smaller area for the architecture is also reported.
  • Keywords
    digital arithmetic; median filters; parallel processing; W/B processing blocks; accumulative parallel counters; median calculation method; median filter architecture; Clocks; Computer architecture; Decoding; Hardware; Radiation detectors; Registers; Vectors; Image Processing; Image processing; Median Filter; Pipelined Processing; median filter; pipelined processing;
  • fLanguage
    English
  • Journal_Title
    Circuits and Systems II: Express Briefs, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1549-7747
  • Type

    jour

  • DOI
    10.1109/TCSII.2015.2415655
  • Filename
    7065320