DocumentCode :
112398
Title :
Error-Correcting Code Aware Memory Subsystem
Author :
Wooyoung Jang
Author_Institution :
Dept. of Electrics & Electr. Eng., Dankook Univ., Yongin, South Korea
Volume :
33
Issue :
11
fYear :
2014
fDate :
Nov. 2014
Firstpage :
1706
Lastpage :
1717
Abstract :
An error-correcting code (ECC) immune to bit errors has been widely used in reliable computer systems. However, ECC techniques can make memory performance severely degraded since incomplete-word write requests lead to inefficient read-to-write (RTW) and write-to-read operations of synchronous dynamic random access memory. In this paper, we propose a memory subsystem efficient for ECC operations. Our key idea is that the RTW operations causing incomplete-word write requests are split and grouped into independent read and write operations, and then the grouped read and write operations are individually scheduled for the optimal memory performance under application constraints. Experimental results show that the proposed ECC-aware memory subsystem achieves 17% shorter memory latency, and 12% higher memory utilization, on average, than the latest conventional memory subsystems on industrial multimedia applications. Moreover, the ECC-aware memory subsystem improves up to 2.5 times higher memory performance on synthetic benchmarks.
Keywords :
DRAM chips; error correction codes; error statistics; ECC-aware memory subsystem; bit errors; error-correcting code; industrial multimedia applications; read-to-write operation; synchronous dynamic random access memory; write-to-read operation; Buffer storage; Clocks; Computers; Error correction codes; Memory management; Reliability; SDRAM; Error-correcting code (ECC); memory subsystem; multimedia system; synchronous dynamic random access memory (SDRAM);
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.2014.2351494
Filename :
6926923
Link To Document :
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