Double-Sampling Design Paradigm—A Compendium of Architectures

Aggressive technology scaling impacts dramatically parametric yield, life-span, and reliability of circuits fabricated in advanced nanometric nodes. These issues may become showstoppers when scaling deeper to the sub-10-nm domain. To mitigate them, various approaches have been proposed, including increasing guard bands, fault-tolerant design, and canary circuits. Each of them is subject to several of the following drawbacks: large area, power, or performance penalty; false positives; false negatives; and insufficient coverage of the failures encountered in the deep nanometric domain. This paper presents various double-sampling architectures, which allow mitigating all these failures at low area and performance penalties and also enable significant power reduction.