Series resistance of devices with submicrometer source/drain areas

Author

Lee, V.V. ; Biellak, S.A. ; Cho, J.S. ; Wong, S. Simon

Author_Institution

Center for Integrated Syst., Stanford Univ., CA, USA

Volume

12

Issue

12

fYear

1991

Firstpage

664

Lastpage

666

Abstract

The source-drain series resistances of devices contacted by a local interconnection technology utilizing polysilicon strapped with selective CVD tungsten were measured and compared to predictions obtained using a theoretical model. Asymmetrical devices in which the local interconnections were intentionally misaligned to the gate were fabricated to study the effects of misalignment on device characteristics. Experiments indicate that the technology is quite forgiving to the misalignment between the gate and the local interconnection.<>

Keywords

CVD coatings; MOS integrated circuits; VLSI; contact resistance; integrated circuit technology; metallisation; tungsten; W strapped polysilicon; contact resistance; device characteristics; effects of misalignment; local interconnection; local interconnection technology; misalignment forgiving technology; polycrystalline Si-W interconnections; selective CVD W metal; source-drain series resistances; submicrometer source/drain areas; Area measurement; Conductivity; Contact resistance; Electrical resistance measurement; Etching; Fabrication; Implants; MOS devices; Physics; Tungsten;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.116948

Filename

116948