Comparison of shallow trench and LOCOS isolation for hot-carrier resistance

Author

Doyle, Brian S. ; O´Connor, Robert S. ; Mistry, Kaizad R. ; Grula, Gregory J.

Author_Institution

Digital Equipment Corp., Hudson, MA, USA

Volume

12

Issue

12

fYear

1991

Firstpage

673

Lastpage

675

Abstract

Hot-carrier stresses were performed on n-MOS transistors with LOCOS and shallow trench isolation. For transistors stressed under the different damage creation conditions, no discernible difference in lifetimes was found for devices down to W/L=3/0.45 mu m. It is shown, however, that the edge of the trench isolation (0.1 mu m wide) is more sensitive to hot carrier effects, having a lifetime up to four times less than the center of the channel. For devices with a W/L ratio of two or less, this could prove problematic. It could also have repercussions for transistors under high-gate-field (Fowler-Nordheim) conditions.<>

Keywords

MOS integrated circuits; VLSI; hot carriers; integrated circuit technology; reliability; LOCOS isolation; damage creation conditions; high gate field conditions; hot carrier effects; hot carrier stresses; hot-carrier resistance; n-MOS transistors; shallow trench isolation; width length ratio; CMOS technology; Etching; Hot carrier effects; Hot carriers; Implants; Isolation technology; Oxidation; Silicon; Stress; Threshold voltage;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.116951

Filename

116951