Control of the performance of polysilicon thin-film transistor by high-gate-voltage stress

Author

Dimitriadis, Charalabos A. ; Coxon, P.A. ; Lowe, A.J. ; Stoemenos, J. ; Economou, N.A.

Author_Institution

Dept. of Phys., Thessaloniki Univ., Greece

Volume

12

Issue

12

fYear

1991

Firstpage

676

Lastpage

678

Abstract

The performance of low-pressure chemical-vapor-deposited (LPCVD) polycrystalline-silicon thin-film transistors (TFTs) can be controlled by applying a high-gate-voltage stress. The potential barrier height at the grain boundary is reduced after positive high-gate-voltage stress and then increases after negative high gate voltage stress. The experimental results indicate that Ca and Al ions or hydrogen atoms existing in the gate oxide may be able to passivate grain boundaries at the polysilicon-SiO/sub 2/ interface.<>

Keywords

CVD coatings; elemental semiconductors; insulated gate field effect transistors; semiconductor-insulator boundaries; silicon; thin film transistors; Al ions; Ca ions; H atoms; LPCVD; MOSFET; Si-SiO/sub 2/; TFTs; experimental results; grain boundary; high-gate-voltage stress; low-pressure chemical-vapor-deposited; passivation; performance; polycrystalline Si; polysilicon thin-film transistor; potential barrier height; Artificial intelligence; Chemicals; Degradation; Electron mobility; Grain boundaries; Hydrogen; Silicon; Stress control; Thin film transistors; Threshold voltage;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.116952

Filename

116952