Eliminating False Lock in Phase-Locked Loops

A model is developed for phase-locked loops incorporating phasefrequency detectors. This model facilitates analysis of the loop and enables us to derive the conditions for false lock. It is shown by analysis that phase-locked loops with phase-frequency detectors are indeed capable of false lock; this theoretical result is verified by experimental results. A method for eliminating false lock is then proposed. This method was implemented in a simple circuit; we present the results of this experiment and show that the method we propose is capable of eliminating false lock.