Title :
GaAs DCFL 2.5 Gbps 16-bit Multiplexer/Demultiplexer LSI´s
Author :
Higashisaka, N. ; Shimada, M. ; Ohta, A. ; Hosogi, K. ; Tobita, Y. ; Mitsui, Y.
Author_Institution :
Optoelectron. & Microwave Devices Lab., Mitsubishi Electr. Corp., Hyogo, Japan
fDate :
7/1/1994 12:00:00 AM
Abstract :
GaAs 2.5 Gbps 16 bit MUX/DEMUX LSI´s have been successfully developed. DCFL is employed as a basic gate in order to reduce the power dissipation. To avoid the speed degradation caused by using DCFL, various technologies such as 8×2(MUX)/2×8(DEMUX) data conversion processes, a Selector Merged Shift Register, clock overlapping, and a 0.7-μm BPLDD MESFET, have been introduced. Moreover the ECL I/O level interface and single power supply features make it easy to use MUX/DEMUX in optical communication systems. The maximum operating data rate is 3.2 Gbps for both LSI´s, and the power dissipation of chips which operates with 2.5 Gbps are as low as 1.3 W for each MUX/DEMUX
Keywords :
III-V semiconductors; demultiplexing equipment; direct coupled FET logic; field effect integrated circuits; gallium arsenide; integrated logic circuits; large scale integration; multiplexing equipment; optical communication equipment; optical receivers; 0.7 micron; 1.3 W; 16 bit; 16-bit multiplexer/demultiplexer LSIs; 2.5 Gbit/s; 3.2 Gbit/s; BPLDD MESFET; DCFL; ECL I/O level interface; GaAs; clock overlapping; data conversion processes; maximum operating data rate; optical communication systems; power dissipation; selector merged shift register; speed degradation; Clocks; Data conversion; Degradation; Gallium arsenide; MESFETs; Multiplexing; Optical fiber communication; Power dissipation; Power supplies; Shift registers;
Journal_Title :
Solid-State Circuits, IEEE Journal of
