DocumentCode :
1132833
Title :
A Logic System for Fault Test Generation
Author :
Akers, Sheldon B.
Author_Institution :
Electronics Laboratory, General Electric Company
Issue :
6
fYear :
1976
fDate :
6/1/1976 12:00:00 AM
Firstpage :
620
Lastpage :
630
Abstract :
This paper describes a logic system specifically designed for fault test generation. The system allows the user to impose a set of initial constraints on the elements of a logic network by indicating those values which an element may (or may not) assume for the test under consideration. He can be as vague or as specific as he wants in imposing these constraints. A set of logic tables is then used to automatically propagate the effects of these constraints throughout the network. As a result of this logic propagtion, the necessary values of the elements in the network become much more precisely (if not completely) defined. The tables also indicate whether or not the generated test (which may include a number of unspecified values) is sufficient to detect the given fault. If several different tests will suffice, the choices remaining are clearly indicated. In the case of a redundant lead (untestable fault), propagation through the tables automatically results in a logical inconsistency.
Keywords :
Fault diagnosis, fault test generation, logic networks, logic systems, stuck-at faults.; Automatic logic units; Automatic testing; Fault detection; Fault diagnosis; Logic design; Logic testing; System testing; Fault diagnosis, fault test generation, logic networks, logic systems, stuck-at faults.;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/TC.1976.1674662
Filename :
1674662
Link To Document :
بازگشت