Title :
Design of Ternary COS/MOS Memory and Sequential Circuits
Author :
Mouftah, H.T. ; Jordan, I.B.
Author_Institution :
Department of Electrical Engineering, University of Toronto
fDate :
3/1/1977 12:00:00 AM
Abstract :
Ternary storage elements are realized using ternary operators and fundamental circuits, designed with the COS/MOS integrated circuits. Several ternary flip-flops (tri-flops) are constructed and described in detail: the PZN (set positive, set zero, and set negative), the clocked PZN, the D-type, and the T-type. Ternary shift registers and ring counter are formed by means of these tri-flops. A master-slave T-type tri-flop is used for the construction of a ternary up counter able to count from 0 to 3n using the normal ternary code or from -(3n-1)/2 to+(3n -1)/2 when the signed-ternary code is employed. With a small modification, a ternary down counter is also constructed. A divide-by-M ternary counter which can be programmed is described. A memory cell is designed for the construction of a ternary random-access-memory array (TRAM). A ternary decoder and encoder are presented to be the elements of a complete ternary read-only memory (TROM). A modified ternary inverter (MTI) is taken as a unit cell of the ternary memory matrix.
Keywords :
COS/MOS integrated circuits, fundamental ternary circuits, multiple-valued logic, programmable divide-by-N counters, ternary counters, ternary flip-flops, ternary logic implementation, ternary memory cells, ternary sequential logic.; Circuit synthesis; Clocks; Delay; Delta modulation; Flip-flops; Lead; Logic; Pulse circuits; Sequential circuits; Switching circuits; COS/MOS integrated circuits, fundamental ternary circuits, multiple-valued logic, programmable divide-by-N counters, ternary counters, ternary flip-flops, ternary logic implementation, ternary memory cells, ternary sequential logic.;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/TC.1977.1674821
