DocumentCode
1136471
Title
Reduction of pump current mismatch in charge-pump PLL
Author
Hwang, M.-S. ; Kim, Jung-Ho ; Jeong, Deog-Kyoon
Author_Institution
Sch. of Electr. Eng. & Comput. Sci., Seoul Nat. Univ., Seoul
Volume
45
Issue
3
fYear
2009
Firstpage
135
Lastpage
136
Abstract
A charge pump that minimises the mismatch between the charging and discharging currents and keeps the currents constant across a wide output voltage range is described. The improved current matching helps reduce the static phase offset and reference spur of a charge-pump phase-locked loop (PLL) and the constant currents help control the PLL dynamics precisely. The proposed charge pump with dual compensation circuits demonstrates current mismatch of less than 3.2% and pump-current variation of 1.7% over the output voltage ranging from 0.2 to 1.0%V in the 0.13%%m CMOS process with 1.2%V supply.
Keywords
CMOS integrated circuits; phase locked loops; CMOS process; charge-pump phase-locked loop; pump current mismatch; pump-current variation; size 0.13 mum; voltage 0.2 V to 1 V; voltage 1.2 V;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:20092727
Filename
4770439
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