Title :
A BiCMOS process utilizing selective epitaxy for analog/digital applications
Author :
O, K.K. ; Lee, Hae-Seung ; Reif, Rafael
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
fDate :
7/1/1989 12:00:00 AM
Abstract :
A 2-μm BiCMOS process that has been designed for 10-V analog/digital applications is described. This process utilizes selective epitaxial growth to integrate a vertical n-p-n bipolar with an fT of 3.0 GHz, and a nonoptimized vertical p-n-p structure into a 2-μm CMOS process with poly-to-n+ capacitors. The insertion of the bipolar structures is accomplished with only two added masking steps, and with no changes to the critical process parameters that determine the performance of the MOS transistors. The circuit worthiness of the process is demonstrated by fabricating CMOS, vertical n-p-n RTL, and vertical p-n-p RTL ring oscillators, and demonstrating high yields for these circuits
Keywords :
BIMOS integrated circuits; integrated logic circuits; large scale integration; semiconductor epitaxial layers; 10 V; 2 micron; BiCMOS process; analog/digital applications; critical process parameters; masking steps; nonoptimized vertical p-n-p structure; poly-to-n+ capacitors; ring oscillators; selective epitaxy; vertical n-p-n RTL; vertical n-p-n bipolar; vertical p-n-p RTL; yields; BiCMOS integrated circuits; Bipolar transistors; CMOS process; CMOS technology; Doping; Epitaxial growth; Epitaxial layers; MOS capacitors; MOS devices; MOSFETs;
Journal_Title :
Electron Devices, IEEE Transactions on
