Title :
A digital filter chip for ECG signal processing
Author :
Raita-aho, Tommi ; Saramäki, Tapio ; Vainio, Olli
Author_Institution :
Signal Process. Lab., Tampere Univ. of Technol., Finland
fDate :
8/1/1994 12:00:00 AM
Abstract :
A VLSI implementation of a linear-phase digital filter for ECG signal processing has been designed. With a sampling rate of 100 Hz, the passband is from 0.5 Hz to 49.5 Hz with 0.5-dB ripple. The filter architecture is based on the use of recursive running-sum blocks, resulting in a very low computational complexity. Module generators have been used in the layout design for high integration density. The circuit has been designed for a 2.0-μm double-metal CMOS technology, having about 34000 transistors and a 15.43-mm2 chip area
Keywords :
CMOS integrated circuits; VLSI; computational complexity; computer architecture; delay circuits; digital filters; digital signal processing chips; electrocardiography; medical diagnostic computing; medical signal processing; ECG signal processing; FIR; VLSI implementation; computational complexity; digital filter chip; filter architecture; integration density; linear-phase digital filter; module generators; recursive running-sum blocks; CMOS technology; Computer architecture; Digital filters; Digital signal processing chips; Electrocardiography; Passband; Process design; Signal design; Signal sampling; Very large scale integration;
Journal_Title :
Instrumentation and Measurement, IEEE Transactions on
