Title :
The effect of the number of defect mechanisms on fault clustering and its detection using yield model parameters
Author :
Collica, Randall S.
Author_Institution :
Digital Equipment Corp., Hudson, MA, USA
fDate :
8/1/1992 12:00:00 AM
Abstract :
The superposition principle is used to analyze faults of different mechanisms. The sum of the individual cluster coefficients of each mechanism is approximately equal to the cluster coefficient for all mechanisms combined. This technique is used on defect density test structures as well as bit failures from SRAM chips. A regression analysis of empirical data is used to demonstrate this concept for the defect density test chips. The actual and, the model fault densities are compared and show excellent agreement. As a comparative analysis, a quadrant technique was used to compile a frequency distribution of electrical faults and a nonlinear least-squares technique is applied to the distribution to estimate the parameters in the gamma and Poisson distributions. These results are compared to the cluster parameters from the summation technique and the technique using moment estimates. All three estimates are in very good agreement. The application of this model to actual chip yields is shown not only to be more accurate but also to contain information about the relative number of fault generating mechanisms for the mask level of interest in the process
Keywords :
electrical faults; failure analysis; integrated circuit manufacture; integrated circuit testing; statistical analysis; IC manufacture; Poisson distributions; SRAM chips; bit failures; cluster coefficient; defect density test structures; defect mechanisms; electrical fault frequency distribution; fault clustering; gamma distribution; nonlinear least-squares technique; quadrant technique; regression analysis; superposition principle; yield model parameters; Circuit faults; Electrical fault detection; Fault detection; Frequency estimation; Integrated circuit manufacture; Integrated circuit modeling; Integrated circuit yield; SRAM chips; Statistics; Testing;
Journal_Title :
Semiconductor Manufacturing, IEEE Transactions on