DocumentCode :
1144507
Title :
Clocking Analysis, Implementation and Measurement Techniques for High-Speed Data Links—A Tutorial
Author :
Casper, Bryan ; Mahony, Frank O.
Author_Institution :
Circuit Res. Lab., Intel Corp., Hillsboro, OR
Volume :
56
Issue :
1
fYear :
2009
Firstpage :
17
Lastpage :
39
Abstract :
The performance of high-speed wireline data links depend crucially on the quality and precision of their clocking infrastructure. For future applications, such as microprocessor systems that require terabytes/s of aggregate bandwidth, signaling system designers will have to become even more aware of detailed clock design tradeoffs in order to jointly optimize I/O power, bandwidth, reliability, silicon area and testability. The goal of this tutorial is to assist I/O circuit and system designers in developing intuitive and practical understanding of I/O clocking tradeoffs at all levels of the link hierarchy from the circuit-level implementation to system-level architecture.
Keywords :
clock and data recovery circuits; data communication; digital communication; input-output programs; phase locked loops; timing jitter; I/O circuit; I/O power; clocking analysis; high-speed wireline data links; microprocessor; silicon area; system-level architecture; Aggregates; Bandwidth; Clocks; Communication system signaling; Design optimization; Measurement techniques; Microprocessors; Power system reliability; Signal design; Tutorial; Clock distribution; clock recovery; high-speed I/O; phase-locked loops;
fLanguage :
English
Journal_Title :
Circuits and Systems I: Regular Papers, IEEE Transactions on
Publisher :
ieee
ISSN :
1549-8328
Type :
jour
DOI :
10.1109/TCSI.2008.931647
Filename :
4774052
Link To Document :
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